Just listen to Jensen (and Lisa): TSMC, Intel, Samsung
Competition for Foundry customers at 2nm / 18A is already over
On one hand we have reports of Samsung securing 2nm customers (Nvidia, Qualcomm), on the other AMD saying that TSMC has the best and only 2nm, Nvidia saying there’s no alternative to TSMC CoWoS.
The competition at 2nm / 18A is already over. Chips are designed and tested, tape-out are rolling out, decisions are finalized. If Intel and Samsung have a chance to gain Foundry customers, it is for the next node, 14A in 2027-28.
The difficulty for Intel and Samsung is that TSMC is a lot faster to develop PDK, qualify process, tape-out chips. The total cost of chip design at US$0.5-1bn is another hurdle.
The facts / news sources are here:
Intel has admitted to “limited customer commitment” at 18A, and not having a Foundry PDK for 14A.
AMD : “TSMC is the leader in the 2nm process, so we are focusing on developing and mass producing it with the highest efficiency per watt and semiconductor performance”
Nvidia answering a journalist question “could Nvidia drop TSMC back-end packaging and use Intel”, answer “because the technology is so advanced, we have no other option to replace TSMC”.
Why is it already too late for Intel and Samsung at 2nm / 18A?
There are 3 major reasons:
Designing and testing a chip requires both EDA and PDK
This process is mostly software-based design and simulations – that’s why it is called Electronic Design Automation (EDA). But the EDA design stage incorporates the Foundry’s PDK. The PDK is a another set of design rules, characteristics of what the manufacturing process can achieve. This means that 3 companies work together: the chip designer (ex Nvidia), the design software provider (EDA software ex Cadence) and the foundry (ex TSMC). This presentation provides a good overview of the imbrication of these actors.
The chart is complicated but illustrates that the software vendors (ex Cadence, Synopsys) EDA is synchronized with the Foundry PDK: the chip designer (Nvidia) needs both.
Design to production takes 24-30 months
You can find many descriptions of the design-to-risk-production process, for ex here or we can listen to TSMC CEO in April 2024:
“we are observing a high level of customer interest and engagement at N2 and expect the number of the new tape-outs from 2-nanometer technology in its first 2 years to be higher than both 3-nanometer and 5-nanometer in their first 2 years”
“there have been a lot of engagement and the tape-out will be higher. N2 is a very complicated work or a very complex technology node. So my customer, they also take a little bit longer time to prepare for the tape-out. So that's why they all engage with TSMC in the early stage”
“we start the N2 production in the second half of 2025, actually in the last quarter of 2025. And because of the cycle time and all the kind of back-end process, and so we expect the meaningful revenue will start from the end of the first quarter or beginning of the second quarter of 2026.”
To summarize:
Design process started before April 2024
Tape-out started in Jan and April 2025
Risk production starts second half of 2025
Mass Volume Production MVP output in 2Q26